1. Field of the Invention
The present invention relates to the fabrication of silicon devices and more particularly to the growing of epitaxial layers of silicon by deposition at low temperatures.
2. Prior Art
Low temperature silicon epitaxial growth processes allow fabrication of novel and small silicon (Si) devices with structures important for high performance semiconductor applications, such as elevated source-drains for CMOS devices, and are key to producing some ultra-fast devices such as the heterojunction bipolar transistors (HBTs) in Si recently reported by G. L. PATTON, S. S. IYER, S. L. DELAGE, S. TIWARI, and J. M. C. STORK, in IEEE EDL, 9, 195 (1990). Important requirements for any potential epitaxial manufacturing process are adequate measures for defect avoidance and control, and broad utility, such as the capability of producing Si layers with necessary additives such as n- and p-type dopants and Ge. Two known low temperature epitaxial processes for Si are disclosed by B. S. MEYERSON in Appl. Phys. Lett., 48, 797 (1986), and T. O. SEDGWICK, M. BERKINBLIT, and T. S. KUAN in Appl. Phys. Lett., 54, 2689 (1989), the former using ultra-high vacuum, chemical-vapor deposition (UHV/CVD) with silane as a reactant, and the latter employing ultra-clean, atmospheric pressure, chemical-vapor deposition (APCVD) using dichlorosilane (DCS) as a reactant. (Here "ultra-clean" means that water vapor, oxygen and other oxidants have been carefully and systematically excluded from the reaction chamber and the gas handling system.) Other systems of this nature are generally disclosed in U.S. Pat. No. 4,592,792 to CORBOY, JR. ET AL and U.S. Pat. No. 4,786,615 to LIAW ET AL. While each of these systems have specific fabrication advantages, they also have definite limitations.